1. Field of the Invention
The present invention relates to a semiconductor device and a method of testing the semiconductor device. In particular, the present invention relates to a semiconductor device in which a semiconductor test is performed through an input buffer or an output buffer before a process of dicing a semiconductor wafer, and a method of testing the semiconductor device.
2. Description of Related Art
In a manufacturing stage, a semiconductor device is required to be tested at a real operation speed. Meanwhile, in recent years, a data transmission speed between the semiconductor device and an external device is getting higher. Therefore, there may be a case where an operation speed of an input/output circuit (input buffer, output buffer) is higher than that of a test signal and thus a test by means of an external tester becomes impossible.
Regarding such a semiconductor device, it is proposed to connect the input buffer and the output buffer of the input/output circuit and to perform a test of the semiconductor device by a loopback method. For example, Japanese Laid-Open Patent Application JP-2001-135687 discloses a semiconductor integrated circuit device, in which a loopback test is performed before a process of dicing a semiconductor wafer.
Referring to FIG. 1, the semiconductor integrated circuit device described in Japanese Laid-Open Patent Application JP-2001-135687 will be explained below. First, a control signal is input to a mode switch terminal 1 and thereby an operation mode is set to a test mode. In the test mode, a selector 6, which receives a normal operation signal output from an internal circuit 7 (output terminal O3-1) and a test signal output from a signal generation circuit 5 (output terminal O1), selects the latter one, i.e. the test signal. The selected test signal is input to a first target input/output buffer 10 (internal input terminal I6). Also, a multiplexer 8 receives a signal from a second target input/output buffer 11 (internal output terminal O7) and outputs the signal not to the internal circuit 7 (input terminal I3-2) but to a signal detection circuit 9 (input terminal I5).
Moreover, another control signal is input to a control terminal 2. This control signal is input to the first target input/output buffer 10 (control terminal CTL6), and to the second target input/output buffer 11 (control terminal CTL7) through an inverter 12. In response to the control signal, the first target input/output buffer 10 is set to an output state while the second target input/output buffer 11 is set to an input state. As a result, a tristate output buffer 10-1 in the first target input/output buffer 10 is set to the output state. Thus, a signal output from the signal generation circuit 5 and input to the internal input terminal I6 is output to a first external pad 15 through the tristate output buffer 10-1. On the other hand, a tristate output buffer 11-1 in the second target input/output buffer 11 is set to a high-impedance state. Thus, a signal input to an external input/output terminal IO7 through a second external pad 16 is input to the multiplexer 8 without being influenced by the tristate output buffer 11-1.
The first external pad 15 and the second external pad 16 are connected with each other through a transmission path 18. Therefore, in the case of the test mode, the test signal output from the signal generation circuit 5 (output terminal O1) is input to the signal detection circuit 9 through the first target input/output buffer 10 (output buffer 10-1), the transmission path 18 and the second target input/output buffer 11 (output buffer 11-2). Further, the test signal is frequency-divided in the signal detection circuit 9 and then output to a test output pad 17 through an output buffer 13.
The test signal output from the test output pad 17 is observed by a test apparatus such as an LSI tester. Consequently, it is possible to check whether or not a circuit operation of the output buffer 10-1 in the first target input/output buffer 10 is normal, to test signal transmission characteristics from the first external pad 15 to the second external pad 16 through the transmission path 18, to check whether or not a circuit operation of the input buffer 11-2 in the second target input/output buffer 11 is normal, and the like.
Referring to FIG. 1, the transmission path 18 (loop path) connecting between the output buffer 10-1 and the input buffer 11-2 is formed on a scribe region 19 of a semiconductor wafer. Therefore, as a result of dicing performed after the test, the transmission path 18 is cut off and hence the first external pad 15 and the second external pad 16 are electrically disconnected from each other. Moreover, after the dicing, a control signal is input to the mode switch terminal 1 and thereby an operation mode is set to a normal operation mode. In the normal operation mode, the first target input/output buffer 10 operates as an output buffer that receives an output signal from the internal circuit 7 and externally outputs the output signal, and the second target input/output buffer 11 operates as an input buffer that transmits an external signal to the internal circuit 7.
The inventor of the present application has recognized the following points. As described above, in the semiconductor integrated circuit shown in FIG. 1, the input buffer and the output buffer are connected with each other through the transmission path 18 formed in the scribe region 19. Therefore, it is possible before the dicing of the semiconductor wafer to test the high-speed operating input/output circuit. After the dicing of the semiconductor wafer, the transmission path 18 between the input buffer and the output buffer is cut off and the input/output circuit operates in the normal operation mode.
However, before the dicing process, the input buffer and the output buffer are always short-circuited through the transmission path 18. Therefore, it is not possible before the dicing to test an output level, an input level, an output impedance, an input impedance and the like. Also, it is not possible before the dicing to perform a function test of a semiconductor device including the input buffer, output buffer and internal circuit.